Torsten
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April 4, 2018 at 01:56 #1439TorstenMember
First: You should use numeric_std from IEEE instead, the std_logic_unsigned or std_logic_signed are proprietary libraries written by Synopsys. For example, see this article by Sigasi for reasons why you should the IEEE libraries instead of the Synopsys ones. If you use VHDL 2008, you can use the numeric_std_unsigned / numeric_std_signed libraries from IEEE. But the main drawback remains: you can only have signed or unsigned operations in one design unit, you can’t use both libraries at the same time.
But I have looked in the source. As their implementation seems only convert to unsigned/signed internally, I see no reason why they should not work with std_logic_vectors bigger than the range of integer type. For example, ‘>’ operator is implemented like this:
function ">"(L: std_logic_vector; R: std_logic_vector) return boolean is
begin
return unsigned(L) > unsigned(R);
end;
January 26, 2018 at 11:20 #1427TorstenMemberThanks, I get far better results with your workaround. If we change the seed function, we could look what kind of hash functions are used for dictionary types in languages like python. I assume, they use functions which are not cryptographic secure, but have a good uniform distribution and are very fast.
But you are right, with such a change, the generated randim numbers are different than before, so we have to carefully think about it. Maybe we should prefer a workaround with less impact. Maybe we could integrate your workaround in a new procedure? As a fast and short term solution? This is the way, I use until we fix this problem …
June 27, 2016 at 07:31 #1172TorstenMemberOne possible work around I found at stack overflow is to use generic types in the entity ports list and to instantiate the generic package with the types included before instantiation of the entity in the architecture: https://stackoverflow.com/questions/16282435/generic-records-vhdl2008
Have to try that with Modelsim later 🙂
May 4, 2016 at 07:44 #1164TorstenMemberThanks Jim for your answer. Your solution is also the way I choose to get it running. Aggregates as a whole seem to be pretty complex. I will try to ask on stack overflow, if someone has an idea.
BTW, see you next week at your course 🙂
March 2, 2016 at 23:56 #1139TorstenMemberLine, as defined in textio package, is string access type:
type line is access string;
When I have strings of unknown length, I also use an access type. But maybe there is another option, which I don’t know…
December 8, 2015 at 03:22 #1090TorstenMemberI also don’t have problems with more than one instance of CovPType when using ModelSim DE 10.4c. However, it is a very simple test bench. Both shared variables of CovPType are not only declarated but also used in the test bench. No problems so far.
Torsten
October 15, 2015 at 05:22 #1061TorstenMemberAs far as I know, you have to create a reference model for your divider by yourself. Maybe in form of precalculated values or with a behavioural model which runs in parallel to the DUV.
October 8, 2015 at 01:16 #1055TorstenMemberThere is a simple example of verifying an adder with OSVVM on EDA playground, maybe this helps.
https://www.edaplayground.com/x/49J
It basically creates a variable of CovPType to generate random stimuli data dependent on coverage holes. The coverage goal is given by BINs with the GenBin and AddCross methods. The simulation finishes when all given bins are hit at least one time, what means that coverage is 100%.
August 18, 2015 at 09:21 #1031TorstenMemberHi Jim,
I tried your advice, now Modelsim prints a error message, which says more about the real problem it has with the code:
#** Fatal: (vsim-3420): Array lengths do not match. Left is (UNDEFINED) (UNCONSTRAINED ARRAY). Right is 0 (1 to 1)
So it seems. that Modelsim cannot handle assignments of constrained strings to a object of unconstrained string type. With unconstrained std_logic_vectors for the data record item, it works.
Torsten
August 18, 2015 at 07:25 #1027TorstenMemberWith older Versions of Riviera Pro on EDA Playground, I get a segmentation fault:
./run.sh: line 7: 23 Segmentation fault (core dumped) vcom ‘-2008’ design.vhd DictP.vhd testbench.vhd
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