Generic packages, unconstrained types and access types
August 18, 2015 at 07:05 #1026
I’m implementing a kind of dictionary type in VHDL-08 for using in simulation. I use ModelSim DE 10.4c.
I’m using a protected type which contains various procedures & functions that form the methods to interact with the dictionary type. The dictionary is implemented as (double) linked list of records entries, a record consists of key, value & access types to last/next entry:
type t_key_ptr is access t_key;
type t_key is record
key : string;
data : G_DATA_TYPE;
last_entry : t_key_ptr;
next_entry : t_key_ptr;
end record t_key;
Until now, the key type was fixed to (unconstrained) string, which works without problems. The type of the value field can be given by a generic list to the package. Now, when I try to make the key field generic also with a second generic type (replace the string type by G_KEY_TYPE in the record above), the simulation fails with a runtime error:
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process: /simulationt/DictP File: ../../DictP.vhd
# Fatal error in Subprogram t_dict.set at ../../DictP.vhd line 52
For me this looks like a memory access error, which could occur when using access types in a wrong way. This error occurs in ModelSim DE 10.4c. The same code works with Riviera Pro 2015.06 on EDA playground.
My question before making a bug report to Mentor is: Is my design valid VHDL-08 code? Or are there restrictions when using generic packages and records with unconstrained types which I didn’t considered?
You can find the test case on EDA playground: https://www.edaplayground.com/x/NniAugust 18, 2015 at 07:25 #1027
With older Versions of Riviera Pro on EDA Playground, I get a segmentation fault:
./run.sh: line 7: 23 Segmentation fault (core dumped) vcom ‘-2008’ design.vhd DictP.vhd testbench.vhdAugust 18, 2015 at 08:46 #1029Jim LewisMember
Can you send me the code at jim at synthworks dot com. I can take a look at it to see what I can.
I have a scoreboard that does all of the above. It works well in 10.3. You may wish to run your test in one of the 10.3 versions. The socoreboard model is a release candidate for OSVVM, so if you send me an email, I will send it to you.
JimAugust 18, 2015 at 09:03 #1030Jim LewisMember
I just remembered a work around for a problem that may apply to your situation.
In VHDL, we can do allocation of this sort of structure as either:
TailPointer := new ListType'(Item1, Item2, Item3, NULL);
TailPointer := new ListType ;
TailPointer.Item1 := Item1;
TailPointer.Item2 := Item2;
TailPointer.Item3 := Item3;
TailPointer.NextPtr := NULL ;
I now use the second one as it seems to work around problems in some simulators.
JimAugust 18, 2015 at 09:21 #1031
I tried your advice, now Modelsim prints a error message, which says more about the real problem it has with the code:
#** Fatal: (vsim-3420): Array lengths do not match. Left is (UNDEFINED) (UNCONSTRAINED ARRAY). Right is 0 (1 to 1)
So it seems. that Modelsim cannot handle assignments of constrained strings to a object of unconstrained string type. With unconstrained std_logic_vectors for the data record item, it works.
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