Steve Chan

*Hi allI am planning to start embedding the more advance assertion contruct in my HDL/TestBench design.My company is generally a VHDL house, but I can foresee use of SV in the future.A mixed language environment is very likely to happen (as a matter it already exist)I have read either PSL or SVA can work in both SV and VHDL.So which assertion…[Read more]

Hi expertA supposing easy question.How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?I was trying to find use assert to compare the std_logic and the input vector in integer.Thanks