Standard VHDL has all the features necessary to code randomization of stimulus and functional coverage – both very important while verifying larger, system-level designs. The problem is that those features are quite advanced and require high coding skills. That’s why Open Source VHDL Verification Methodology is so important. It creates a couple of easily accessible VHDL packages that hide quite arcane implementation details from the average user, making generation of random stimulus and intelligent functional coverage not only easy, but also pleasurable task.
Question: Do you prefer to write a lot of code to get the desired result or would you rather write intelligent code that gets you to the same result faster? Check out OS-VVM and its intelligent testbench concept that creates feedback between randomization and functional coverage procedures…
Benefits of OS-VVM
- Based on VHDL 2008, can work with VHDL 2002
- Provides advanced capabilities for random value generation and functional coverage
- Randomizes values with uniform or weighted distributions
- Also supports favor_small, favor_big, Gaussian and Poisson distribution
- Works perfectly with Transaction Level Modeling
- Enables intelligent randomization based on the functional coverage holes (bins that are not covered)
- Allows definition of normal, illegal and ignore bins for regular coverage and cross-coverage
- Equipped with flexible coverage reporting procedures
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