Verification capability is largely a matter of programming. VHDL is a capable programming language. Like SystemVerilog, writing directly in VHDL is tedious and potentially error prone. Open Source VHDL Verification Methodology (OSVVM) provides a methodology and library to simplify the entire verification effort. OSVVM supports the same capabilities that other verification languages support – from transaction level modeling, to functional coverage and randomized test generation, to data structures, and to basic utilities. The intention of OSVVM goes beyond capability though – OSVVM intends to make verification environments easy, readable, and fun.
Capabilities of OSVVM
OSVVM offers the same capabiities as those based on other verification languages.
- Transaction-Level Modeling
- Constrained Random test generation
- Functional Coverage with hooks for UCIS coverage database integration
- Intelligent Coverage Random test generation
- Utilities for testbench process synchronization
- Transcript files
- Error logging and reporting – Alerts and Affirmations
- Message filtering – Logs
- Scoreboards and FIFOs (data structures for verification)
- Memory models
Other verification languages have sacrificed ease of use and readability for capability. As a result, they require a specialist to both create a basic environment and write a test. Going further to use their verification features, you must have a license that supports those features. OSVVM demonstrates that you can have capability, simplicity, and conciseness all from one language and a methodology. In addition, all OSVVM features are created in the free, open-source library and do not require any special licensing beyond requiring VHDL-2008 support.
OSVVM is maintained by volunteers. In addition to using this methodology, you can contribute by providing feedback to make it better.
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