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OSVVM Webinar and Class Dates

April 3, 2018 in Alerts and Logs, OS-VVM in general

Webinar Taming Testbench Messaging and Error Reporting with OSVVM’s Logs and Alerts.

Thursday April 5, 2018

Printing and error reporting in VHDL are tedious, yet necessary testbench tasks. Fortunately, Open Source VHDL Verification Methodology (OSVVM) provides library utilities to simplify these tasks. This presentation covers the details of OSVVMs transcript utility in TranscrptPkg as well as OSVVM’s logs, alerts, and affirmations in AlertLogPkg.

Testbench printing consists of messages from different entities. To collect the output from different sources into a single file will generally result in the usage of OUTPUT and intermingling of test results with simulator messages. OSVVM transcripts allow the collection of all test outputs into either OUTPUT or a named file.

Printing in VHDL involves TEXTIO which requires multiple calls to write followed by a call to writeline. OSVVM focuses on printing type string and uses the VHDL-2008 to_string functions to handle any necessary conversions. Hence, simple printing is a single call to print.

Going further will test the need to filter messages. Only print a particular message during the debug. Print another message when testing is complete and we need printing to document what tests were run and passed. OSVVM is capable of handling this through its logging utility.

Error handling in tests can be complicated and error prone. Error handling involves printing (the easy part) and error counting. Unfortunately, the error counting requires a separate signal for each process that can detect an error. When the test completes, we sum up all of the error sources and print a pass / fail report. OSVVM handles error counting and printing via its Alert and Affirm procedures. When one of these detects an error, it records it in a data structure that is inside the AlertLogPkg. When the test completes, the test writer calls ReportAlerts and a pass/fail report is produced.

Europe Session 3-4 pm CEST 6-7 am PST 9-10 am EST Enroll with Aldec
US Session 11 am -12 noon PST 2-3 pm EST 8-9 pm CEST Enroll with Aldec

OSVVM Training Dates

Advanced VHDL Testbenches and Verification – OSVVM+ Boot Camp

Like the Webinar? Ready to make Open Source VHDL Verification Methodology (OSVVM) part of your VHDL testbench and verification methodology? Join me for Advanced VHDL Testbenches and Verification, AKA The OSVVM Boot Camp.

In this class you will gain hands on experience in the latest VHDL verification techniques using OSVVM. You will create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. These techniques and capabilities include:
• Transaction-Based Modeling
• Constrained Random test generation
• Functional Coverage with hooks for UCIS coverage database integration
• Intelligent Coverage Random test generation
• Utilities for testbench process synchronization
• Transcript files
• Error logging and reporting – Alerts and Affirmations
• Message filtering – Logs
• Scoreboards and FIFOs (data structures for verification)
• Memory models

Our techniques work on VHDL simulators without additional licenses and are intended to be readable by Verification and RTL design engineers, as well as, system and software engineers.

The intention of OSVVM goes beyond capability though – OSVVM intends to make verification environments easy, readable, and fun. OSVVM can accomplish this for either a large complex ASIC or a simple FPGA RTL block.

Join us – learn to work smarter and not harder. Expect to work hard in class though as this is a 5 day class and our typical class day is 8 hours (8:30 – 17:30+)

April 23 – 27 and May 7 – 11 Web Class Enroll with SynthWorks
May 21 – 25 Gothenburg, Sweden Enroll with FirstEDA
June 4 – 8 and June 18 – 22 Web Class Enroll with SynthWorks

OSVVM: Webinar and Training

October 2, 2017 in Alerts and Logs, Announcement, Event, Functional Coverage, OS-VVM in general, Randomization, Transaction Based Testbench

Webinar OSVVM: ASIC Level Verification, Simple Enough for FPGAs. Thursday October 5, 2017

Just because your design is complex does not mean your testbench needs to be. With Open Source VHDL Verification Methodology (OSVVM), we have found that with proper abstractions we can create simple, readable, and powerful testbenches – and we can even have some fun while doing it.

OSVVM provides an ASIC level VHDL verification methodology that is simple enough to use even on small FPGA projects. OSVVM offers the same capabilities as those based on other verification languages:
• Transaction-Based Modeling
• Constrained Random test generation
• Functional Coverage with hooks for UCIS coverage database integration
• Intelligent Coverage Random test generation
• Utilities for testbench process synchronization
• Transcript files
• Error logging and reporting – Alerts and Affirmations
• Message filtering – Logs
• Scoreboards and FIFOs (data structures for verification)
• Memory models

OSVVM is implemented as a library of free, open-source packages. It uses these packages to create features that rival language based implementations in both conciseness, simplicity, and capability.

Looking to improve your FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece is separate and can be used separately. Hence, you can learn and adopt pieces as you need them.

This presentation will be a broad overview of each of OSVVM’s capabilities. While Transaction Based Modeling and Scoreboards were released to OSVVM in 2016, they are mature capabilities that have been used for over 10+ years now in SynthWorks’ VHDL Training classes.

Europe Session 3-4 pm CEST 6-7 am PST 9-10 am EST Enroll with Aldec
US Session 11 am -12 noon PST 2-3 pm EST 8-9 pm CEST Enroll with Aldec

OSVVM Training Dates

Advanced VHDL Testbenches and Verification – OSVVM+ Boot Camp

Like the Webinar? Ready to make Open Source VHDL Verification Methodology (OSVVM) part of your VHDL testbench and verification methodology? Join me for Advanced VHDL Testbenches and Verification, AKA The OSVVM Boot Camp.

In this class you will gain hands on experience in the latest VHDL verification techniques using OSVVM. You will create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. These techniques and capabilities include:
• Transaction-Based Modeling
• Constrained Random test generation
• Functional Coverage with hooks for UCIS coverage database integration
• Intelligent Coverage Random test generation
• Utilities for testbench process synchronization
• Transcript files
• Error logging and reporting – Alerts and Affirmations
• Message filtering – Logs
• Scoreboards and FIFOs (data structures for verification)
• Memory models

Our techniques work on VHDL simulators without additional licenses and are intended to be readable by Verification and RTL design engineers, as well as, system and software engineers.

The intention of OSVVM goes beyond capability though – OSVVM intends to make verification environments easy, readable, and fun. OSVVM can accomplish this for either a large complex ASIC or a simple FPGA RTL block.

Join us – learn to work smarter and not harder. Expect to work hard in class though as this is a 5 day class and our typical class day is 8 hours (8:30 – 17:30+)

October 16 – 20 and October 30 – November 3 Web Class Enroll with SynthWorks
November 6 – 10 Bracknell, UK Enroll with FirstEDA
November 27 – December 1 and December 11 – 16 Web Class Enroll with SynthWorks

Transcripts, Alerts, and Logs

April 7, 2015 in Alerts and Logs, OS-VVM in general

Transcripts, Alerts, and Logs are the focus of the 2015.01 and 2015.03. What are these all about?

Transcript Files

OSVVM’s transcript capability simplifies having different parts of a testbench print to a common transcript file. It does this by providing an internal file identifier (TranscriptFile), and subprograms for opening (TranscriptOpen) files, closing (TranscriptClose) files, printing (print and writeline), and checking if the file is open (IsTranscriptOpen).

Read more at: Testbench Transcripting

Alerts

OSVVM’s AlertLogPkg simplifies and formalizes the signaling errors (at run time), counting errors, and reporting errors (summary at test completion). Indication of an error is done via a call to one of the Alert procedures (Alert, AlertIf, AlertIfNot, AlertIfEqual, AlertIfNotEqual, or AlertIfDiff). Alerts have the levels FAILURE, ERROR, or Warning. Each level is counted and tracked in an internal data structure. Within the data structure, each of these can be enabled or disabled. A test can be stopped if an alert value has been signaled too many times. Stop values for each counter can be set. At the end of a test, the procedure ReportAlerts prints a report that provides pass/fail and a count of the different alert values.

Read more at: Using Alerts

Logs

Logs provide a mechanism to conditionally print information. Verbosity control allows messages that are too detailed for normal testing to be printed when specifically enabled. Logs have the levels ALWAYS, DEBUG, FINAL, and INFO.

Read more at: Using Logs