Summary of 2023.04 Changes Updated co-simulation environment to support both Streaming Interfaces as well as Address Bus Interfaces. More details in a future post by Simon Script settings are now split between OsvvmScriptSettings.vhd which has deferred constants and a generated package body OsvvmScriptSettings_Generated.vhd (which is in the .gitignore) – Thanks Philip Updated Interrup... »
By Simon Southwell, OSVVM CoSim Technical Lead Introduction I have written previously about co-simulation in my series of LinkedIn articles about using the programming interfaces of logic simulator tools in a fairly generic way, summarising the possibilities and referencing, in outline, some real-world use cases. Since then, I have been collaborating to bring some of these co-simulation features t... »
Summary of 2023.01 Changes Co-simulation environment that supports running software (C++) in a hardware simulation environment. Added OsvvmScriptSettings.vhd to the OSVVM utility library. Autogenerated when the OSVVM library is analyzed. Script settings with the OSVVM library Added Interrupt generator and updated interrupt handling. Added PassThru VC for Axi4, Axi4Lite, and AxiStream to act... »
Summary of 2022.12 Changes Updated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found Updated scripts for Synopsys VCS and Cadence Xcelium Updated log file creation to first use OsvvmBuild.log and then it is copied to “LogFileDirectory”/”BuildName”.log. Updated Generic Handling Both Simulate and RunTest support callin... »
As I was writing the blog about the 2022.10 Multiple Verification Component example, my focus was drawn to the issue, “How do I call transactions that iterate across an array of verification components?” Solving this issue became the main goal of the 2022.11 release. The 2022.11 release includes: Updated Multiple Verification Component Test Example Created AddressBus and Stream transac... »
Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas. For the 2022.10 release, I prepared a basic example that instances 16 UartTx and UartRx components. The good thing about writing test cases like this is that it reveals further opportunities for improvements. As I wrote this a... »
Summary of recent changes in OSVVM. Added Ethernet Phy and MAC verification components for GMII, RGMII, MII, RMII Added interrupt handler that supports any verification component that uses the Address Bus Model Independent Interface RandomPkg: added SetRandomSalt as a method to add an offset to all InitSeed calculations – Thanks Torsten M Added demo of using multiple OSVVM VC using “fo... »
Don’t miss your chance to express what verification approach you use for FPGAs (OSVVM) This is the first public survey I have seen. Others have been done by random selection and invitation only. Survey is here »
On GitHub Issues, I had the following question, “With OSVVM scripting (.pro), is there a way to specify testbench generics, waveform files, and length of time to run a simulation.” So lets take a look at these. Lets add to that, where do I get help on OSVVM from? Specifying Generics Every simulator has their own format for specifying generics. With OSVVM, we specify generics by calling... »
Summary of recent changes in OSVVM: Scripts updated for better signaling to continuous integration (CI) tools MemoryPkg updated to remove 31 bit limitation and support storage policies. Reports keep getting better Scripts now support simulating with two top level designs Scripts updated to better support GHDL options and waveforms Scripts now support callbacks to simplify user customization Script... »