VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment

IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing.

Language changes were use model driven and had multiple opportunities to be pruned from implementation. The process started with a discussion of feature requests. Feature requests were then voted on and ranked. High ranked features were discussed and developed into proposals. Proposals were required to provide use models to affirm their worth and validity. Proposals were then developed into language change specifications (LCS).

The entire process was driven by volunteers – and again almost all were users. Volunteerism added another level of scrutiny to each request and/or proposal. If no one was willing to write a proposal or an LCS for an item, then no matter how high the feature or proposal was ranked, it failed to be worthy of being implemented.

In Part 1 of VHDL-2019: Just the New Stuff series, we will explore:

• Interfaces
• Conditional Compilation
• File IO Updates
• Environment Package Updates (Partial Selection)

Interfaces allow abstract connections between designs. Ever wanted to encapsulate all signals of an interface into a single record only to be confounded by not being able to specify the direction of elements of the record? Well now you can.

Conditional compilation. Users have requested this numerous times. Finally done!

The File IO updates include file open state, rewind, and file position.

The Environment package updates include Directory operations, access to Date and Time, and access to environment variables.

VHDL-2019 was requested by users, ranked by users, scrutinized by users, written by users, and balloted by the VHDL community. As such, it should be clear to the vendor (simulator and synthesis) community that the users want these features.

Aldec started their implementation of VHDL-2019 prior to the standard being completed and is well into their implementation. If your vendor cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will.

What about Verilog and SystemVerilog? It is clear from the Wilson Verification survey that VHDL is the preferred FPGA design language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM.

The VHDL standards committee work is never done. It takes a collaboration of people with different skills to successfully update the standard. Some of these members are language experts, some design experts, and some verification experts. Join us in writing the next revision. See: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome.

Presenter BIO

The presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design, verification, and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.

Whether teaching, developing OSVVM, doing VHDL design or verification consulting, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.

Enroll