Announcing Release 2022.09+

Summary of recent changes in OSVVM:

• Scripts updated for better signaling to continuous integration (CI) tools
• MemoryPkg updated to remove 31 bit limitation and support storage policies.
• Reports keep getting better
• Scripts now support simulating with two top level designs
• Scripts updated to better support GHDL options and waveforms
• Scripts now support callbacks to simplify user customization
• Scripts updated for better error handling
• Scripts now handle Verilog libraries in during compile

 
For specific itemized changes in each release, see the OSVVM downloads page.

Have ideas for what you would like added or updated next in OSVVM, you can share your ideas at on OSVVM forums, on GitHub Issues, or send me email at jim at synthworks.com. Keep in mind that email can get lost, so you may need to be more persistent.

Want to contribute to OSVVM? Pull requests are accepted on GitHub. Please first submit and issue so we can discuss what you would like to do first.

Some of these deserve a full blog post, so I just provide a brief overview below.

Scripts updated for better signaling to CI tools

Error reporting to the CI tools is controlled by the following variables. The values shown are their defaults.
variable FailOnBuildErrors "true"
variable FailOnReportErrors "false"
variable FailOnTestCaseErrors "false"
variable AnalyzeErrorStopCount 0
variable SimulateErrorStopCount 0

If there is an error during the build (such as analyze or simulate), and FailOnBuildErrors is true, then the build will signal an error. If there is a report error during the build (such as one of the reports failed), and FailOnReportErrors is true, then the build will signal an error. If there is a test case fails during the build (ie: test did not PASS), and FailOnTestCaseErrors is true, then the build will signal an error.

If AnalyzeErrorStopCount is 0, then if an analyze error occurs, the build will continue until it gets to its normal ending point. If AnalyzeErrorStopCount is non-zero, then the build will end with an error if AnalyzeErrorStopCount analyze errors occur.

If SimulateErrorStopCount is 0, then if an simulation error occurs, the build will continue until it gets to its normal ending point. If SimulateErrorStopCount is non-zero, then the build will end with an error if SimulateErrorStopCount simulation errors occur.

OSVVM uses GHDL to run regressions as a GitHub Action.

MemoryPkg updated to remove 31 bit limitation and support storage policies.

The 31 bit data width limitation is an artifact of using type integer to store values and the “original” X mapping policy. In the “original” X mapping policy, if there was an X in any bit, the entire word became X.

MemoryPkg now supports an unlimited number of bits and maintains bitwise fidelity of X’s. MemoryPkg_NoX supports an unlimited number of bits and maps X to 0 – potentially reducing the size of the storage required for the memory. MemoryPkg_orig is limited to 31 bits and supports the “original” X mapping policy.

Reports keep getting better

Since creating the HTML reports in 2021.10, they keep getting better. A couple of changes that have happened over the last couple releases include:

• Scoreboard reports are now done as a row in a single table
• A “mini” build summary is produced in text when a build finishes
• The HTML simulator transcript now shows errors in red text making them easier to find

Scripts now support simulating with two top level designs

Many commercial simulators allow you to load multiple top level designs into the simulator. If you are using some FPGA vendor libraries, they use the second top for some of their Verilog settings.

Scripts updated to better support GHDL options and waveforms

When running simulate in GHDL, the location of the options depends on whether the option is an elaborate option or a run option. The new API commands SetExtendedElaborateOptions and SetExtendedRunOptions allow settings to be put in the proper place for simulators like GHDL.

Calling “SetSaveWaves true” will result in saving waveforms in the file “TestbenchName”.ghw in the directory Reports/”TestSuiteName”.

Scripts now support callbacks to simplify user customization

Callbacks in the form CallbackBefore_”ApiCmd” and CallbackAfter_”ApiCmd” are supported for library, build, include, analyze, and simulate. For details, see OsvvmLibraries/Scripts/CallbackDefaults.tcl.

Scripts updated for better error handling

Error handling is now done as a callback in the form of CallbackOnError_”Cmd”. This moved all of the error handling to the same place and made error handling more uniform.

Scripts now handle Verilog libraries during compile

When compiling a Verilog design, one must identify the resource libraries to the simulator. As a VHDL person, this requirement is a strange requirement since we do not have to do this for VHDL simulators. No worries, OSVVM automatically adds the libraries when calling analyze.

1 Comment

1. 

   Torsten October 28, 2022, 15:06 Log in to Reply

   Ha, very nice.

   In my current system test bench of a AXI-QDMA Interface I model memory using my own dictionary implementation. First I used plain `std_logic_vector`, but it became slower & slower with increasing writes to new addresses in the dict. Then I’ve remembered that integers are “faster” than values with 9-state logic. So I’ve done something similar to your MemoryPkg, using an `integer_vector(0 to 1)` to store 64-bit wide `std_logic_vector` values, and also using integers for the address in the dictionary.

   I’ve looked into an older version of your MemoryPkg before, which was limited to 31 bit – which was the reason for my own memory implementation. Now that this restriction is gone, it’s maybe finally time to try OSVVMs MemoryPkg.

   Greetings,
   Torsten