LibraryUnit adding scripts to simulate

Why OSVVM™? Forums OSVVM LibraryUnit adding scripts to simulate

Viewing 5 posts - 1 through 5 (of 5 total)
  • Author
    Posts
  • #2171
    Li
    Member

    Hi OSVVM fans,

    I am new to this method and have just created my first project. I need to use a .tcl file to initialize a RAM. The following description I have found:

    Adding Scripts to Simulate
    Often with simulations, we want to add a custom waveform file.
    This may be for all designs or just one particular design.
    We may also need specific actions to be done when running
    on a particular simulator.
    When simulate (or RunTest) is called, it will source the following files in order, if they exist:

    <ToolVendor>.tcl
    <ToolName>.tcl
    wave.do
    <LibraryUnit>.tcl
    <LibraryUnit>_<ToolName>.tcl
    <TestCaseName>.tcl
    <TestCaseName>_<ToolName>.tcl

    ToolVendor is either {Aldec, Siemens, Cadence, Synopsys}.
    ToolName is one of {QuestaSim, ModelSim, RivieraPRO, ActiveHDL, VCS, Xcelium}.
    LibraryUnit is the name specified to simulate.
    TestCaseName is the name specified to TestCase.

    I don’t quite understand what is LibraryUnit name here. I’d appreciate it if someone can explain it more to me. Thanks!
    Li

    #2172
    Jim Lewis
    Member

    LibraryUnit in this case is the name which you used with simulate, hence, either the name of your testbench or configuration that runs your testbench. Often, I try to make this the same as the TextCaseName, but it does not have to be.

    In VHDL, LibraryUnit is an analyzed Design Unit and from the LRM,

    A design unit is
    either an entity declaration, an architecture body, a configuration declaration, a package declaration, a
    package body, a package instantiation declaration, a context declaration, or a PSL verification unit. (13.1)

    #2175
    Li
    Member

    Hi Jim,

    thanks for the explanation. I tried to post some more detail but I got this:
    A potentially unsafe operation has been detected in your request to this site
    Your access to this service has been limited. (HTTP response code 403)

    If you think you have been blocked in error, contact the owner of this site for assistance.

    Block Technical Data
    Block Reason: A potentially unsafe operation has been detected in your request to this site
    Time: Thu, 30 Mar 2023 15:55:06 GMT
    About Wordfence
    Wordfence is a security plugin installed on over 4 million WordPress sites. The owner of this site is using Wordfence to manage access to their site.

    You can also read the documentation to learn about Wordfence’s blocking tools, or visit wordfence.com to learn more about Wordfence.

    Click here to learn more: Documentation

    Generated by Wordfence at Thu, 30 Mar 2023 15:55:06 GMT.
    Your computer’s time: Thu, 30 Mar 2023 15:55:06 GMT.

    #2176
    Li
    Member

    Hi Jim,

    thanks for the explanation. If I make the .tcl script the TestCaseName, it will be sourced and the RAM is successfully initialized during the simulation. But I think it is sourced as <TestCaseName>.tcl but not <LibraryUnit>.tcl. Because with any other name it will not be sourced, at least in my project. I have tried testbench name, package name and so on. They don’t work.

    #2177
    Li
    Member

    I just want to post my test_harness.pro and testbench.pro files here so you may understand me more clearly. But every time I post the code, it is rejected. How can I post a code segment here? I have tried the “CODE” button, but it still does not work.

Viewing 5 posts - 1 through 5 (of 5 total)
  • You must be logged in to reply to this topic.