Reply To: About function coverage of OS-VVM by vector signal

One more thing: your code samples coverage data on the same clock edge that triggers counting. It means that currect active clock edge samples data triggered by previous active clock edge. The side effect is that your code will never display results containing anything in bin 7, because database dump condition is reached before “111” data can be sampled. You can use either delayed clock for sampling or sample on the other clock edge. The code that should let you get full coverage is presented below:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std_unsigned.all;
use work.CoveragePkg.all;

entity counter is
 port (CLK : in std_logic ;
       RST : in std_logic ;
       OUTA : out std_ulogic_vector (2 downto 0)
 ) ;
end counter ;

architecture RTL of counter is
  signal cnto :std_logic_vector(2 downto 0);
  shared variable test_cover : CovPType ;

begin

test_cover.AddBins(GenBin(0,7,8));

process (CLK,RST) begin
  if RST='0' then
    cnto <= (others=>'0') ;
  elsif (CLK'event and CLK='1') then
    cnto <= cnto + '1';
  end if ;
end process ;

process (CLK) begin
  if (CLK'event and CLK='0') then
    test_cover.ICover(to_integer (cnto));
  end if;
end process ;

process (CLK) begin
  if (CLK'event and CLK='1') then
    if (cnto="111") then
      test_cover.WriteCovDb ("test_cover.txt", OpenKind => WRITE_MODE );
      test_cover.WriteBin;
    end if ;
  end if;
end process ;

OUTA <= cnto;

end RTL ;