About function coverage of OS-VVM by vector signal

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  • This topic has 4 replies, 2 voices, and was last updated 9 years ago by kuri.
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  • #206
    kuri
    Member

    Hi,

    I’m trying function coverage of OS-VVM by vector signal.
    However, I think that the result isn’t correct.
    I created simple sample.?Please see following.

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    library ieee ;
    use ieee.std_logic_1164.all ;
    Use ieee.std_logic_unsigned.all;
    use work.CoveragePkg.all;

    entity counter is
    port (CLK : in std_logic ;
    RST : in std_logic ;
    OUTA : out std_ulogic_vector (2 downto 0)
    ) ;
    end counter ;

    architecture RTL of counter is
    signal cnto :std_logic_vector(2 downto 0);
    shared variable test_cover : CovPType ;

    begin

    test_cover.AddBins(GenBin(0,7,8));

    process (CLK,RST) begin
    if RST=’0′ then
    cnto ‘0’) ;
    elsif (CLK’event and CLK=’1′) then
    cnto WRITE_MODE );
    test_cover.WriteBin;
    end if ;
    end if;
    end process ;

    OUTA <= cnto;

    end RTL ;

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    When this design is simulated, the following result is obtained.

    1 8
    1 6 1 1 6.000000e+002 0 0
    1 4 1 1 4.000000e+002 1 1
    1 0 1 1 0.000000e+000 2 2
    1 0 1 1 0.000000e+000 3 3
    1 0 1 1 0.000000e+000 4 4
    1 0 1 1 0.000000e+000 5 5
    1 0 1 1 0.000000e+000 6 6
    1 0 1 1 0.000000e+000 7 7

    Could you send the advice for obtaining the correct result?

    #208
    kuri
    Member

    Is the escape of HTML necessary for this forum?

    library ieee ;
    use ieee.std_logic_1164.all ;
    Use ieee.std_logic_unsigned.all;
    use work.CoveragePkg.all;

    entity counter is
    port (CLK : in std_logic ;
    RST : in std_logic ;
    OUTA : out std_ulogic_vector (2 downto 0)
    ) ;
    end counter ;

    architecture RTL of counter is
    signal cnto :std_logic_vector(2 downto 0);
    shared variable test_cover : CovPType ;

    begin

    test_cover.AddBins(GenBin(0,7,8));

    process (CLK,RST) begin
    if RST='0' then
    cnto <= (others=>'0') ;
    elsif (CLK'event and CLK='1') then
    cnto <= cnto + '1';
    end if ;
    end process ;

    process (CLK) begin
    if (CLK'event and CLK='1') then
    test_cover.ICover(to_integer_vector (cnto));
    end if;
    end process ;

    process (CLK, cnto) begin
    if (CLK'event and CLK='1') then
    if (cnto="111") then
    test_cover.WriteCovDb ("test_cover.txt", OpenKind => WRITE_MODE );
    test_cover.WriteBin;
    end if ;
    end if;
    end process ;

    OUTA <= cnto;

    end RTL ;

    #223
    Ian Gibbins
    Keymaster

    Kuri,

    Two issues with your code:

    1. You are using ‘std_logic_unsigned‘ package which can cause serious problems when mixed with VHDL-2008 code. Long story short: if your system contains ‘std_logic_unsigned‘ precompiled in VHDL-2002 mode and you try to use it together with OS-VVM packages compiled in VHDL-2008 mode, logic types internal markers in the libraries will be incompatible in both. You may get no errors/warnings during your design compilation, or receive confusing messages stating that subprograms cannot be found for given argument types. Please use NUMERIC_STD_UNSIGNED that was added to VHDL-2008 specifically for the same purposes as ‘std_logic_unsigned‘, but avoids numerous problems in the older package.
    2. Once you replace package in the design unit header, there is one more issue left: you are creating 8 INTEGER bins, so the data sampled in the data collection process should be INTEGER, not INTEGER_VECTOR. Please replace test_cover.ICover(to_integer_vector (cnto)); with test_cover.ICover(to_integer (cnto));.

    After those two changes you should get correct results.

    BTW, the replies in Forums are treated as HTML code (with different tags allowed for different levels of users). List of allowed tags is always presented below the entry field. It means that not allowed tags will be stripped before posting, and ‘less than’ and ‘greater than’ characters may be treated as parts of tag. You can either escape those characters, or in case of VHDL code export it to HTML from some popular editor (Notepad++, Programmer’s Notepad, etc.) and then paste exported HTML to the reply.

    #226
    Ian Gibbins
    Keymaster

    One more thing: your code samples coverage data on the same clock edge that triggers counting. It means that currect active clock edge samples data triggered by previous active clock edge. The side effect is that your code will never display results containing anything in bin 7, because database dump condition is reached before “111” data can be sampled. You can use either delayed clock for sampling or sample on the other clock edge. The code that should let you get full coverage is presented below:

    library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.numeric_std_unsigned.all;
    use work.CoveragePkg.all;

    entity counter is
     port (CLK : in std_logic ;
           RST : in std_logic ;
           OUTA : out std_ulogic_vector (2 downto 0)
     ) ;
    end counter ;

    architecture RTL of counter is
      signal cnto :std_logic_vector(2 downto 0);
      shared variable test_cover : CovPType ;

    begin

    test_cover.AddBins(GenBin(0,7,8));

    process (CLK,RST) begin
      if RST='0' then
        cnto <= (others=>'0') ;
      elsif (CLK'event and CLK='1') then
        cnto <= cnto + '1';
      end if ;
    end process ;

    process (CLK) begin
      if (CLK'event and CLK='0') then
        test_cover.ICover(to_integer (cnto));
      end if;
    end process ;

    process (CLK) begin
      if (CLK'event and CLK='1') then
        if (cnto="111") then
          test_cover.WriteCovDb ("test_cover.txt", OpenKind => WRITE_MODE );
          test_cover.WriteBin;
        end if ;
      end if;
    end process ;

    OUTA <= cnto;

    end RTL ;

    #235
    kuri
    Member

    Hi Jerry-san

    Thank you for your advice.
    I could collect the correct data.

    Thanks,
    kuri

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