Reply To: The #if in VHDL

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July 12, 2024 at 15:22 #2524
Jim Lewis
Member

Hi Hassan,
It is part of VHDL-2019. It is called Conditional Analysis. I have heard that vendors support it in older revisions. Even vendors who make no claims about supporting VHDL-2019.

For details, see my presentation, VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and Environment. I did this through Aldec as one of their events. You should be able to register with them and watch it.

For the example from the presentation, see: https://gitlab.com/synthworks/VHDL_2019 then ConditionalAnalysis

Best Regards,
Jim