Reply To: Safer Check if Simulation passed or Not

Hi Mikael,
This is a good point. In VHDL-2019, we put things in that will allow OSVVM to collect error information from VHDL and PSL assertions. Sounds like a great addition for the next release.

Do you know which version of Questa started supporting the following subprograms from std.env:
For VHDL Asserts:
GetVhdlAssertCount, IsVhdlAssertFailed, ClearVhdlAssert, IsVhdlAssertFailed,
SetVhdlAssertEnable, GetVhdlAssertEnable
For PSL:
PslAssertFailed, PslIsCovered, ClearPslState

With these OSVVM should be able to report these directly in our reports.

In the VHDL-2019 presentation, I am lead to believe these are at least supported in the current version.

Best Regards,
Jim