OSVVM 2026.01

The OSVVM 2026.01 release adds one big feature, PCIe CoSim Verification Component, and numerous smaller updates.
 

PCIe CoSim Verification Component
OSVVM now has a co-simulation based PCIe Verification Component thanks to Simon Southwell’s hard work. This reverses the typical co-simulation relationship where software communicates through the MIT interface to an OSVVM VHDL VC. Instead, with the PCIe CoSim Verification Component, the VC is implemented on the software side and is able to be interacted with via the MIT transaction interface from the OSVVM test sequencer.
 

MIT – DoDirectiveTransactions
Added a DoDirectiveTransactions procedure for AddressBus and Stream interfaces that implements common directive transactions. Updated Axi4Full, AxiStream, AxiLite, UART, and Wishbone to use this.

Step by step OSVVM is reducing the work required to create a VC.
 

VHDL-2019 interface
Added VHDL-2019 interface capability to Address Bus MIT and AXI4 Full VC. Support for interfaces in Stream MIT is deferred to later revision due to simulator vendor support issues.
 

AXI4 Full VC
Updated AXI4 full to support VHDL-2019 interfaces. This results in 4 separate architectures – one for 2019, one for Vti 2019, one for 2008 and one for Vti 2008. The entities were separated from the architectures as the interface rarely changes – now there is an Axi4Manager_e.vhd (for the entity) and Axi4Manager_a.vhd (for the architecture).

If you need to edit the architecture, only edit the VHDL-2019 architecture which is in Axi4/src. Instead of updating the others, set the TCL variable OsvvmDevDeriveArchitectures “true” in OsvvmSettingsLocal.tcl. Then run the Axi4 build.pro and the architectures are automatically generated.
 
ScoreboardGenericPkg
Updated FindAndFlush and FindAndDelete such that if the item is found, it reports as a PASSED and otherwise as FAILED.
 

Opening the TestCase File
Test case reports provide a link to the test case file with the assumption that the test case file was immediately analyzed before the simulate was called. By default, clicking on the link opens the file in the browser. Setting the Tcl variable VhdlFileViewerPrefix (in your OsvvmSettingsLocal.tcl) to “vscode://file/” will result in the file opening in vscode.
 

Test Case Alert Reports
For VHDL-2019 simulators, the VHDL Assert counts are reported as an alert ID in the Alert report.
 

Language Support Package
Added the constant, TOOL_USES_32_BIT_INTEGERS, that is true when the simulator supports 32 bit integers and false if the simulator supports 64 bit integers.

 
Updated build error handling
By default OSVVM catches all errors and does not generate Tcl errors when exiting.
This is desirable as when running CI, you want all test cases that can run to run.
When running CI, use the JUnit test reporter to generate pass/fail messages.
 
Adding the following tcl variables to your OsvvmSettingsLocal.tcl will adjust OSVVM’s Tcl error signaling:

• FailOnBuildErrors – Signal a tcl error if an error was signaled during a build. Default is false.
• FailOnReportErrors -Signal a tcl error if an error was signaled during reporting. Default is false.
• FailOnTestCaseErrors – Signal a tcl error any test case fails during a build. Default is false.
• AnalyzeErrorStopCount – if 0, do not signal Analyze errors, otherwise, signal analyze error (and stop) when AnalyzeErrorStopCount errors occur. Default is 0.*
• SimulateErrorStopCount – if 0, do not signal Simulate errors, otherwise, signal simulate error (and stop) when SimulateErrorStopCount errors occur. Default is 0*

If you have errors in any part of the OSVVM process, adjust the following TCL variables

• TclDebug – When true and an OSVVM API command fails, print Tcl’s $::errorInfo when an error occurs. Default false.
• ReportDebug – When true and OSVVM reporting fails, print Tcl’s $::errorInfo when an error occurs. Default false.

 
Note: SetInteractiveMode will change both AnalyzeErrorCount and SimulateErrorCount to 1 and Debug to true (which the same impact as TclDebug).
 

Generating Compile Lists as TOML and CSV List
Added CreateDryRunDist, CreateAnalyzeListCsv, and CreateVhdlLsToml to the script API to

• CreateDryRunDict – Instead of running analyze and simulate, collect file list and simulate list as dictionaries.
• CreateAnalyzeListCsv – Run in DryRun and produce a inorder CSV list of files
• CreateVhdlLsToml – Run in DryRun and produce VHDL LS Toml files.

Build Summary Report Updates
If a test suite has 0 PASSED, 0 FAILED, and 0 SKIPPED, the suite reports as EMPTY.

If the analyze immediately before a simulate fails, the simulate will not start and the test will report that the analyze failed.

When simulate is run interactively, it runs as if build were called and a set of reports is created and linked into the Index of Builds report.
 

Scripts & 2019 Features
Added VHDL-2019 feature controls. These are set automatically in the VendorScripts_***.tcl file. SetVHDLVersion 2019 automatically done for tools that support it. Turn 2019 off by doing SetVHDLVersion 2008 in your OsvvmSettingsLocal.tcl
 
Report Stuff
Updated YAML output to better collaborate with https://github.com/edaa-org/pyEDAA.OSVVM