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*Hi allI am planning to start embedding the more advance assertion contruct in my HDL/TestBench design.My company is generally a VHDL house, but I can foresee use of SV in the future.A mixed language environment is very likely to happen (as a matter it already exist)I have read either PSL or SVA can work in both SV and VHDL.So which assertion…[Read more]

Hi all,from RandomPkg.vhd  ref.: 2.1* constant NULL_INTV : integer_vector (0 downto 1) := (others => 0);Modelsim gives ** Warning: [3] ../packages/RandomPkg.vhd(92): (vcom-1246) Range 0 downto 1 is nullNULL_INTV is used as init value, but why with this empty range ?Bug, Feature ?

Hi expertA supposing easy question.How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?I was trying to find use assert to compare the std_logic and the input vector in integer.Thanks  

I recently downloaded the OSVVM package and was looking it over.  Something that was striking was the naming conventions in the packages which seemed, to me, somewhat inconsistent.For an example, I am looking at RandomPkg.vhd in the package declaration.  One observation is that VHDL is insensitive to case, so DISTTYPE is the same as DistType.…[Read more]

Hi,This post is to discuss a planned change to RandCovPoint.  Its current declaration is:impure function RandCovPoint ( PercentCov : real := 100.0 ) return integer_vector ;Currently PercentCov is used to enable two separate concepts.  If PercentCov is greater the current minimum coverage, then PercentCov represents a coverage goal.  Anything…[Read more]

Hi,Can the cyclic random like the randc of SystemVerilog be described in OS-VVM?I think that I describe it by using the function coverage and RandCovPoint method.Is this idea correct?best regards,kuri

I see that OS-VVM is using protected types internally at the quite advanced level. I have done my share of coding in VHDL but am not very familiar with this type of construct. Any suggestions how to improve my understanding?