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The Report APIs should be there in Questa sim 2025.2.
The latest Questasim version is now 2025.3

Remember that today, mixed language designs are very common. Some IPs are only available in Verilog.
So it is not just VHDL assertions that can be a source of errors.
There could be SVA assertions, both immediate and concurrent.

IPs or library…[Read more]

Hi Mikael,
This is a good point. In VHDL-2019, we put things in that will allow OSVVM to collect error information from VHDL and PSL assertions. Sounds like a great addition for the next release.

Do you know which version of Questa started supporting the following subprograms from std.env:
For VHDL Asserts:
GetVhdlAssertCount,…[Read more]

By saving the UCDB file for each testcase (<testname>.ucdb , you can also check the teststatus afterwards:

>vcover attribute OsvvmTemp_Questa/TbAxi4_DemoMemoryReadWrite1.ucdb

The tcl procedure I use to check the test status,just contact me and I will send it. Seems like the code is blocked.

Is there any update on this i.e can we now generate the reports of OSVVM from VUnit test framework based testbench?

Ok, I found it, need to use depricated module LanguageSupport2019Pkg_c.vhd – there is overloaded “to_string” function inside.

Still have problem, but it looks that problematic is “to_String” function, because full Error string stand as folow:

ERROR: [VRFC 10-9439] type error near ‘l’; expected type ‘direction’ [x:/x/x/OsvvmLibraries/osvvm/AlertLogPkg.vhd:4525]
ERROR: [VRFC 10-2922] ‘to_string’ expects 1 arguments [x:/x/x/OsvvmLibraries/osvvm/AlertLogPkg.vhd:4525]
ERROR:…[Read more]

I think the problem is “integer_vector” type. It looks like it is invisible in AlertLogPkg package.
I don’t know why.
Did someone had the some issue?