Activity

Does OSVVM also provide message passing mechanism like the VUnit does, for creation of BFMs?

Jim,

Good to know. My apologies for the confusion. I was referencing OSVVM version 2024.03.

That is good news for me, since I run the tools in a Linux environment.

Thanks for the quick response. I’ll keep experimenting on my end.

-Jake

Hi Jake,
Sorry. In my last post I thought maybe there was a 2024.03 for Siemens.

I am testing on Windows. My contact at Siemens says there are issues with running OSVVM in Visualizer version 2024.01. So at least for Windows we are waiting for the next release of Visualizer. I understand that these issues are not a problem on the Linux…[Read more]

Short answer is yes. OSVVM VC (including AXI4) use items from the other OSVVM libraries, so you will need to compile those.
To build OSVVM, I recommend using the the OSVVM-Scripts. Then in VUnit you can map the OSVVM libraries.

OSVVM VC report errors against the OSVVM AlertLogPkg. You will either want to use the OSVVM AlertLogPkg in your…[Read more]

> 1. Do the OSVVM VC for these AMBA busses support all parts of the specification for these busses?
That is certainly the intent.

> 2. What is the difference between the OSVVM VC for these busses and the ones from UVVM?
I will only talk about the OSVVM VC as I don’t pay attention to the UVVM VC.

All OSVVM VC use the OSVVM Model Independent…[Read more]

Hi Jake,
Are you running on Linux or Windows? Currently I am testing on Windows. My contact at Siemens says there are some issues with running OSVVM in Visualizer in 2024.01. As a result, I had not put the effort into running it just yet. However I have not heard from him about 2024.03. I will check.

Best Regards,
Jim

Jim,

Any updates on this? I’ve looked through the tcl scripts for the newest release (2024.03) and don’t seem to see any visualizer support yet.

Thanks for your time,
Jake

“A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.”. What does this really mean that it cannot be build with AXI-Interface in VHDL? AXI interface is just bunch of signals and the design will eventually get mapped to FPGA pins and compiled to get netlist and bitstream. Why should VHDL AXI interface…[Read more]

What does your interface look like? Are there any control signals? When do you receive a result – immediately or several clocks later? What operations does it support? What is the set of values you intend to apply to your ALU to verify it?

2024.03a addresses this issue – specifically when running interactively, EndSimulation will not be called.