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Javid became a registered member 1 year, 2 months ago
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Colin became a registered member 1 year, 2 months ago
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Joseph replied to the topic Test case issue in the forum OSVVM 1 year, 2 months ago
This is resolved now. The problem was I was calling the VC directly instead of WRITE or READ, which calls the operations in my VC.
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Jake became a registered member 1 year, 2 months ago
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Colin became a registered member 1 year, 2 months ago
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Beepo became a registered member 1 year, 2 months ago
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Joseph started the topic Test case issue in the forum OSVVM 1 year, 2 months ago
Hi I’m having an issue trying to make a testcase for a proprietary protocol. I’m using Questa Sim. When compiling the testcase file, I get these errors: # ** Error: ../testcases/file.vhd(92): (vcom-1348) Prefix (enumeration literal “WRITE_OP”) of indexed name is not an array.
# ** Error: ../testcases/file.vhd(94): (vcom-1348) Prefix (enumeration…[Read more] -
Jacob became a registered member 1 year, 2 months ago
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Nolan became a registered member 1 year, 2 months ago
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Javid became a registered member 1 year, 2 months ago
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Jens became a registered member 1 year, 2 months ago
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Fabio became a registered member 1 year, 2 months ago
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Abdulkadir became a registered member 1 year, 2 months ago
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Jake replied to the topic Questa Verilog/SystemVerilog Files in the forum OSVVM 1 year, 2 months ago
Yep, making the change as you outlined fixed the issue for me. Thanks Jim for the quick response!
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Jim Lewis replied to the topic Questa Verilog/SystemVerilog Files in the forum OSVVM 1 year, 2 months ago
Hi Jake,
Just checked the Questa command reference manual. Good catch. It is an easy fix.
In the file, VendorScripts_Siemens.tcl, all of the specialization is done. In there
the analyze for Verilog/SystemVerilog is:
`tcl
proc vendor_analyze_verilog {LibraryName FileName args} {
set AnalyzeOptions [concat [CreateVerilogLibraryParams “-l…[Read more] -
Jake started the topic Questa Verilog/SystemVerilog Files in the forum OSVVM 1 year, 2 months ago
Hello,
I’ve observed the following warnings when using the analyze command to compile Verilog/SystemVerilog files that are part of my DUT into an OSVVM environment.
“Warning: (vlog-13461) More than 1 logfile is specified using -l/-logfile. The last specified logfile … will only be considered for printing logs”
I’m using OSVVM 2023.09b and…[Read more]
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Peter became a registered member 1 year, 2 months ago
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michel became a registered member 1 year, 2 months ago
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Isaac became a registered member 1 year, 2 months ago
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Tobias became a registered member 1 year, 2 months ago
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