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Thanks for the insight.

VUnit is an exisiting framework which is part of the current CI pipeline setup I use. Currently most of the testbenches use VUNIT HDL as well as the automation test runner features for CI.

As mentioned, looking to benefit from the OSVVM features especially VCs, functional coverage and reporting to enable a comprehensive…[Read more]

Hi Alex,
What is your motivating factor to use VUnit? Is there some capability there that you would like to see in OSVVM? Are you just using VUnit as a test runner or are you also using some of the VHDL code that is part of VUnit?

Currently OSVVM HTML reports are collaboration of OSVVM scripting and OSVVM VHDL code. The Test Case reports are…[Read more]

Hi Ajeetha,
I had started a reply right away and thought I had finished, but apparently forgot to submit it.

TCover in OSVVM is does transition coverage. You will need to name your something different.

It is ok to use the existing data structure for TCover to record the last value. I think your check is off a little as yours currently will…[Read more]

Thanks Jim, that helped. Now I have a running VUNIT testbench with the AXI4Lite VC. I would like to further extend this with the reporting features. I did browse through the scripting docu and the examples about the reporting. I am able to generate the YAML files. But the HTML reports are missing. Since I run a VUNIT testbench is there anything…[Read more]

OSVVM supports 2 processes for interrupt handling. See https://github.com/OSVVM/Documentation/blob/main/InterruptHandler_user_guide.pdf for details.

It uses 2 separate records. Control flow automatically switches to the interrupt handling process when an interrupt is pending. As described in the user guide it requires a specific interrupt…[Read more]

I use the Axi4Lite Manager as a master to access an AXI slave in the DUT. I need a solution to access the AXI slave from both the processes whcih I an currently not able to because of the multiple detect error. The AXI slave does have a memory as well as register map for configuration. And the interrupt comes from the slave indicating an arriving…[Read more]

Can you describe what you are doing.

While you can release the record there are other approaches.

For interrupt handling, OSVVM has an interrupt handler. See the common (MIT) repository in OsvvmLibraries.

You can also directly access OSVVM memories – no transaction record required

Out teaching OSVVM this week so it is harder to give…[Read more]

Hi Charles,
Currently OSVVM does not have control of where the Xilinx library goes. While we want it to go in the VHDL_LIBS directory, currently it is not.

Once we have control of where the library is, then to have two projects share the same compiled image of OsvvmLibraries we need to have a separate place for the OsvvmLibraries and the…[Read more]

Actually both, to have a robust test.

For the former, just to be clear, , I have an AxiStreamReceiver and I am testing my DUT which has an axis master. So, I want to assert in the TestCase tready before tvalid or after tvalid (1, 2, n clock cycles). Is that what you meant? Is there any example to follow?

Do you need this as strict “on” and “off” for tready or do you need e.g. random back-pressure on the bus?

I think for the latter we need @JimL answer. For the former, you can setup a coverage model, which acts as a distribution function. This CovModel can be handed over to the receiver to randomly accept data or delay reception.