Activity – Open Source VHDL Verification Methodology

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Nigel replied to the topic Weird QuestaSim Base Error in the forum OSVVM 1 month, 2 weeks ago

Hi Jim,

Thanks for that. I had noticed from other questions that this may have been the issue.
Strangely, I am actually using Questa 2024.3 with OSVVM 2025.06a and I get the issue. As suggested I placed “SetVHDLVersion 2008” in my sim script and everything worked just fine.

Cheers,

Nigel
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Jim Lewis replied to the topic OSVVM: Build part of design and run only single test in the forum OSVVM 1 month, 2 weeks ago

Hi Hassan,
What version of OSVVM are you using? The current version is 2025.06a.
What simulator and version are you using?

> 1. When only the testbench code was compiled. Why did it say “failed”?
Perhaps you can share the log files with me so I can look at it. Ultimately I need a reproducer test case of this.
Also try puts $::…[Read more]
Hassan started the topic OSVVM: Build part of design and run only single test in the forum OSVVM 1 month, 2 weeks ago

Here are the steps:

First compile everything.
build ../OsvvmLibraries/OsvvmLibraries.pro
…

Later just compile the DUT, lets say that it is the AXI4.
build ../OsvvmLibraries/Axi4/Axi4/build.pro

Now compile the testbench for this DUT:
build ../OsvvmLibraries/Axi4/Axi4/testbench/build.pro

Now run single test:
RunTest…[Read more]
Jim Lewis replied to the topic Weird QuestaSim Base Error in the forum OSVVM 1 month, 2 weeks ago

Hi Nigel,
In the OSVVM 2024.09 and 2025.02 releases, the 2019 compile switch was turned on if the Questa release is greater than 2024.2. With the OSVVM 2025.04a release and beyond the 2019 switch it is turned back off again. So I recommend getting the newest release of OSVVM (2025.06a) and this problem is resolved.

In Questa, your issue is…[Read more]
Jim Lewis replied to the topic Weird QuestaSim Base Error in the forum OSVVM 1 month, 2 weeks ago

Hi Nigel,
In the OSVVM 2024.09 and 2025.02 releases, the 2019 compile switch was turned on if the Questa release is greater than 2024.2. With the OSVVM 2025.04a release and beyond the 2019 switch it is turned back off again. So I recommend getting the newest release of OSVVM (2025.06a) and this problem is resolved.

In Questa, your issue is…[Read more]
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Nigel started the topic Weird QuestaSim Base Error in the forum OSVVM 1 month, 2 weeks ago

Got a bit of a strange one here. I finally had to bite the bullet and let go of ModelSim DE and upgrade to QuestaSim Base. Straight away I ran into a problem with my simulations that use OSVVM (my sims that don’t use OSVVM work fine). When running the sim, Questa reports the following error:

** Error:…[Read more]
Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 1 month, 2 weeks ago

The Report APIs should be there in Questa sim 2025.2.
The latest Questasim version is now 2025.3

Remember that today, mixed language designs are very common. Some IPs are only available in Verilog.
So it is not just VHDL assertions that can be a source of errors.
There could be SVA assertions, both immediate and concurrent.

IPs or library…[Read more]
Jim Lewis replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 1 month, 2 weeks ago

Hi Mikael,
This is a good point. In VHDL-2019, we put things in that will allow OSVVM to collect error information from VHDL and PSL assertions. Sounds like a great addition for the next release.

Do you know which version of Questa started supporting the following subprograms from std.env:
For VHDL Asserts:
GetVhdlAssertCount,…[Read more]
Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 1 month, 2 weeks ago

By saving the UCDB file for each testcase (<testname>.ucdb , you can also check the teststatus afterwards:

>vcover attribute OsvvmTemp_Questa/TbAxi4_DemoMemoryReadWrite1.ucdb

The tcl procedure I use to check the test status,just contact me and I will send it. Seems like the code is blocked.
Mikael started the topic Safer Check if Simulation passed or Not in the forum OSVVM 1 month, 2 weeks ago

Today the outcome of the simulation is solely dependent on the OSVVM report server and if you have triggered an error or not.
But if you have for example an external library cell/ip that uses assertions, it can still look as the simulation passed while it indeed failed.

I added “assert false” in a testcase to illustrate the problem. This is the…[Read more]
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