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Hi Adam,
If C_PHY_GEN_TRUE is a top level generic, OSVVM will allow you to specify it for either simulate or RunTest. As long as your simulator supports that, it should work just fine. Generate is resolved at elaboration time – which is the first step of simulation.

Have you tried something like this and it failed to work?

Jim

Okay, this is very helpful information and from this I believe the answer to what I am trying to do is probably no.

Looking at TestStandAlone.vhd assume there is a generate statement that decides if xMiiPhy gets created or not.


phy_gen : if C_PHY_GEN_TRUE = 1 generate

xMiiPhy_1 : xMiiPhy
generic map (
MII_INTERFACE =>…[Read more]

In OsvvmLibraries/Ethernet/TestStandAlone/TestStandAlone.pro, I set the generics for the top level test by doing:

simulate Tb_xMii1 [generic MII_INTERFACE RGMII] [generic MII_BPS BPS_1G]

Here Tb_xMii1 is the name of the configuration for the testharness (named TbStandAlone).

So if you have not already, add top level generics to the…[Read more]

Hey,

glbl is a verilog file referenced by an IP from a third party vendor.

Is it possible to set a generic for a file that is analyzed before simulation? Looking at the script users guide I would think that SetExtendedAnalyzeOptions is meant to accomplish this but I could be using the command incorrectly. Is it possible to use…[Read more]

Have you tried:

simulate DUT_test glbl -L unisim [generic C_EXAMPLE_PARAM 1]

What library is glbl in? If it were VHDL and glbl is in the unisim library, the glbl would be referenced as unisim.glbl.

If all of your simulations nee glbl and unisim library, you can do

SetExtendedSimulateOptions "-L unisim"
SetSecondSimulationTopLevel…[Read more]