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Hi Jim,

thanks for the explanation. I tried to post some more detail but I got this:
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LibraryUnit in this case is the name which you used with simulate, hence, either the name of your testbench or configuration that runs your testbench. Often, I try to make this the same as the TextCaseName, but it does not have to be.

In VHDL, LibraryUnit is an analyzed Design Unit and from the LRM,

A design unit is
either an entity…

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