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Oliver replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 2 years, 5 months ago
Hi Jim,
thanks for the link. Now that I finally got my tools working I will have a look at it soon. The OSVVM demo tests look good and run well (not when following the old user’s guide in the OSVVM Examples zip archive on this site though). Unfortunately the simulation of Xilinx PCIe-demo-design with Vivado will not run when the language is set to…[Read more] -
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Adrian Simionescu's profile was updated 2 years, 5 months ago
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Yacine became a registered member 2 years, 5 months ago
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Jim Lewis wrote a new post 2 years, 6 months ago
Summary of 2022.12 ChangesUpdated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found
Updated scripts for Synopsys VCS and Cadence Xcelium […]
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Christophe became a registered member 2 years, 6 months ago
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