Activity
-
Jim Lewis wrote a new post 3 years, 1 month ago
For some time now, OSVVM has been doing releases every month. Sometimes I talk about them, sometimes they just get posted to the downloads page.
Over the past several releases OSVVM has:
Im […]
-
Paul changed their profile picture 3 years, 1 month ago
-
Lukas became a registered member 3 years, 1 month ago
-
Alexander became a registered member 3 years, 1 month ago
-
Lukas became a registered member 3 years, 1 month ago
-
Mason became a registered member 3 years, 1 month ago
-
Alexander became a registered member 3 years, 1 month ago
-
omaima started the topic Ordre of stimulus in the forum OSVVM 3 years, 1 month ago
Hello hope you all are doing well,
I have a DUT of an adder which take 2 values as input and calculate the addition .
I have written an OSVVM testbench for this , as an exercice in familiarizing myselef with osvvm , and I have some questions.
To generate the values of the inputs I called the procedure GenBin 2 times inside the AddCross procedure…[Read more] -
Steve became a registered member 3 years, 1 month ago
-
Mohamed became a registered member 3 years, 1 month ago
-
Bry became a registered member 3 years, 1 month ago
-
CHRISTOPHE became a registered member 3 years, 1 month ago
-
Mike became a registered member 3 years, 1 month ago
-
Keith became a registered member 3 years, 1 month ago
-
Markus replied to the topic Race conditions / buffer issues in console output in the forum OSVVM 3 years, 1 month ago
It seems the problem was on my end after all
When I call
vsim -batch -do "build project.pro"
the output is fine. However, when I call it with a pipeline operator to postprocess the output
vsim -batch -do "build project.pro" | cat
the output is somehow mixed up.This is a buffering problem which can be solved with unbuffer:
unbuffer -p vsim -batch…
[Read more] -
Markus started the topic Race conditions / buffer issues in console output in the forum OSVVM 3 years, 1 month ago
I had troubles concerning the order of console output, esp. in combination with ModelSim/Questasim.
Problem Description:
Assume the following proc in VendorScript_Mentor.tcl (pseudocode):
proc analyze {FileName} {
puts Starting VCOM
vcom ... $FileName
puts VCOM Done
}I got the following output:
Starting VCOM
VCOM Done
…
<actual output…[Read more] -
Paul became a registered member 3 years, 1 month ago
-
Steve became a registered member 3 years, 1 month ago
-
Ahmed became a registered member 3 years, 1 month ago
-
Ahmed became a registered member 3 years, 1 month ago
- Load More