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Markus replied to the topic Race conditions / buffer issues in console output in the forum OSVVM 3 years, 1 month ago
It seems the problem was on my end after all
When I call
vsim -batch -do "build project.pro"
the output is fine. However, when I call it with a pipeline operator to postprocess the output
vsim -batch -do "build project.pro" | cat
the output is somehow mixed up.This is a buffering problem which can be solved with unbuffer:
unbuffer -p vsim -batch…[Read more] -
Markus started the topic Race conditions / buffer issues in console output in the forum OSVVM 3 years, 1 month ago
I had troubles concerning the order of console output, esp. in combination with ModelSim/Questasim.
Problem Description:
Assume the following proc in VendorScript_Mentor.tcl (pseudocode):
proc analyze {FileName} {
puts Starting VCOM
vcom ... $FileName
puts VCOM Done
}I got the following output:
Starting VCOM
VCOM Done
…
<actual output…[Read more] -
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Michael replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
Thanks for all the support Jim!
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