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Michael replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
Thanks for all the support Jim!
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Jim Lewis replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
I have pushed the updated code to the main branch now.
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Jim Lewis replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
Hi Michael,
Unfortunately this impacts all OSVVM VC. So the same change is needed for the UartTx.Are you using sources from OSVVM.org or GitHub? I have updated the GitHub dev branch. I will update the main branch tomorrow. If you are using sources from OSVVM.org, I will update them too, otherwise, they will be updated when 2022.05 is…[Read more]
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Michael replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
I went ahead and changed the code and it fixed the issue. Thank you!
One more quick question, my DUT also does the reverse… takes data from 21 UARTs and mux’s it all to one serial output. So while I haven’t gotten around to it yet, the next part of my test bench is going to have 21 UART_TX VC’s in it.
Would I be correct in assuming that I…[Read more]
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Michael replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
Thanks for the quick response Jim! I will try to get it working on my end in the meantime, just for the sake of getting deeper into the weeds with OSVVM.
I am simulating with Aldec Riviera Pro v.2019.10
Regards,
Michael - Load More