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Roman became a registered member 5 years, 1 month ago
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Gary's profile was updated 5 years, 1 month ago
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David Clift wrote a new post 5 years, 2 months ago
In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage […]
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Hi David,
Thanks for nice post, it is quite useful.
I have a few comments:
1. If we want fewer lines of the code, we can combine Bins using concatenation &, for example :— Test21
FSM_CP.AddCross(“Test21”, GenBin(BlackJack_type’POS(Test21)),
GenBin(BlackJack_type’POS(BustState)) & GenBin(BlackJack_type’POS(HoldState)) & GenBin(BlackJack_type’POS(TenBack)));2. As an alternative to the approach in the post,
it is good idea to separate the coverage model and the coverage collector in two processes:COVERAGE_MODEL: process
begin
— Begin_g
FSM_CP.AddCross(“Begin_g to Hit_me”,
GenBin(BlackJack_type’POS(Begin_g)),
GenBin(BlackJack_type’POS(H1_Hit_me)));
.
.
.
— Mark rest as illegal.
FSM_CP.AddCross(ALL_ILLEGAL, ALL_ILLEGAL);
wait;end process COVERAGE_MODEL;
COVERAGE_COLLECTOR: process
constant COMBINATIONAL_DELAY : time := 1 ns;
alias current_state is <>;
alias next_state is <>;
beginwait until rising_edge(clk);
wait for COMBINATIONAL_DELAY;
— update coverage information
v_fsm_transition_coverage.ICover( (BlackJack_type’POS(current_state), BlackJack_type’POS(next_state)) );end process COVERAGE_COLLECTOR;
Regarding the external names used in COVERAGE_COLLECTOR process, it is assumed that RTL code of the FSM contains the process for FSM state register.
Something as:STATE_REG: process(clk, reset_n)
begin
if reset_n = ‘0’ then
current_state <= Begin_g;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process STATE_REG;Best regards,
Miroslav -
Hi Miroslav,
Thank you for your kind comments and encouragement, I am glad my post was helpful, hopefully you will find my upcoming post useful as well.
With regards to your questions:
1. Could you use concatenation to shorten the code? Probably, I haven’t tried it. Typically I tend to write things out longhand so to speak, as you see here each stage is clearly separated. This helps with understandability and maintainability.
2. Using two processes once for the coverage model and another for the coverage collector, the important thing is to ensure all the collection bins are built at time zero, this happens when the process gets evaluated at time zero (All process run to their first wait). I am not sure of the benefit of splitting the coverage model into two parts.Maybe I will discuss this with Jim next time we speakKeep safe
David…
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Jim Lewis wrote a new post 5 years, 2 months ago
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from t […]
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