Activity
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Jim Lewis wrote a new post 12 years, 8 months ago
Why no constraint solver? Are you going to add one?Nope. No constraint solver. Instead OS-VVM implements an innovative “Intelligent Testbench” feature that does a random walk across functional cove […]
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vio123 started the topic ../packages/RandomPkg.vhd(92): Range 0 downto 1 is null in the forum OSVVM 12 years, 8 months ago
Hi all,from RandomPkg.vhd ref.: 2.1* constant NULL_INTV : integer_vector (0 downto 1) := (others => 0);Modelsim gives ** Warning: [3] ../packages/RandomPkg.vhd(92): (vcom-1246) Range 0 downto 1 is nullNULL_INTV is used as init value, but why with this empty range ?Bug, Feature ?
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Steve Chan started the topic How to compare compare std_logic and integer in the forum VHDL 12 years, 9 months ago
Hi expertA supposing easy question.How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?I was trying to find use assert to compare the std_logic and the input vector in integer.Thanks
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Brian Padalino started the topic Coding/Naming Conventions in the forum OSVVM 13 years, 2 months ago
I recently downloaded the OSVVM package and was looking it over. Something that was striking was the naming conventions in the packages which seemed, to me, somewhat inconsistent.For an example, I am looking at RandomPkg.vhd in the package declaration. One observation is that VHDL is insensitive to case, so
DISTTYPE
is the same asDistType
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Jim Lewis started the topic RandCovPoint(0.0) and potential changes in the forum OSVVM 13 years, 3 months ago
Hi,This post is to discuss a planned change to RandCovPoint. Its current declaration is:impure function RandCovPoint ( PercentCov : real := 100.0 ) return integer_vector ;Currently PercentCov is used to enable two separate concepts. If PercentCov is greater the current minimum coverage, then PercentCov represents a coverage goal. Anything…[Read more]
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kuri started the topic About cyclic randomlike the randc of SystemVerilog in the forum OSVVM 13 years, 3 months ago
Hi,Can the cyclic random like the randc of SystemVerilog be described in OS-VVM?I think that I describe it by using the function coverage and RandCovPoint method.Is this idea correct?best regards,kuri
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Ian Gibbins started the topic How to handle protected types in the forum VHDL 13 years, 4 months ago
I see that OS-VVM is using protected types internally at the quite advanced level. I have done my share of coding in VHDL but am not very familiar with this type of construct. Any suggestions how to improve my understanding?