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Jim Lewis wrote a new post 5 years, 10 months ago
I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop […]
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Phil's profile was updated 5 years, 10 months ago
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Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years, 10 months ago
Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.
Best Regards,
Jim -
Cahit's profile was updated 5 years, 10 months ago
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Ken Campbell started the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years, 10 months ago
Hello everyone.
I just wanted to point out, and correct me if I am wrong, OSVVM is the only method that has Intelligent Coverage Random test generation. SV does not. This is a major plus for OSVVM.
If in fact only OSVVM provides this feature, I think it should be more obviously stated as a step above or an advantage over other methods.
Ken
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Tobias's profile was updated 5 years, 10 months ago
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Jim Lewis wrote a new post 5 years, 10 months ago
Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between […]
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Evert Scholtz's profile was updated 5 years, 10 months ago
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Ian Gibbins wrote a new post 5 years, 10 months ago
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.
While your EDA vendor may […]
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