Author: David Clift

OSVVM FSM Coverage Modelling

David Clift June 12, 2020 Functional Coverage, OS-VVM in general, Randomization 2

In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage model for the Blackjack state machine shown in figure 1: The aim of our functional model is to create a coverage bin for each state transition so we can ensure that during our tests, every ... »

External Names; Beyond the scope of VHDL

David Clift May 19, 2020 VHDL in general 0

There are many things that differentiate VHDL from Verilog. One example, is the ability to use global signals in Verilog, which enables a signal at the top-level to connect to one or more points in the hierarchy. This particular feature is used very effectively by Xilinx, to distribute the Global Set/Reset signal GSR to their IP and cell simulation models. The signal is generated in the glbl.v, wh... »