Introduction In the previous OSVVM co-simulation article, I wrote about debugging co-simulation programs with GDB and how to add an IDE on top of this to give full dual debug capability with a software IDE, such as Eclipse, working alongside a GUI based logic simulator, such as Riviera-PRO or QuestaSim. This was about debugging the program that’s running on an OSVVM co-simulation node. One of the ... »
Introduction Co-simulation features were added to OSVVM at release 2023.01. This allows C or C++ code to be compiled for the machine hosting a logic simulator to be run as part of a logic simulation and interact with that simulation via a provide API, and I have written an introductory blog on osvvm.org in the past and there is, of course, a manual. With the introduction of software into a logic s... »
Introduction With the 2026.01 release of OSVVM a new verification component (or VC) was added to support the PCI Express (PCIe) bus protocol. OSVVM already has a comprehensive suite of VCs for both memory mapped address bus protocols, such as AXI, and streaming protocols, such as Ethernet. The PCIe VC extends OSVVM’s supported protocols as part of its ongoing development. However, there is somethi... »
Introduction The OSVVM Co-simulation features allow user supplied C or C++ code to drive model independent transaction (MIT) signals in a VHDL logic simulation via a supplied API, as I’ve discussed in a previous blog. When combined with one of the supplied Verification Components (VCs) or with a custom VC, the user software can generate protocol specific signalling to drive a design under te... »
Introduction The OSVVM co-simulation environment has the ability to generate transactions from C++ to drive various virtual components (VCs), such as AxiBus, AxiStream, Ethernet, Uart, dual port RAM etc. But did you know that you can drive multiple VCs from within the same test bench, all driven by C++ software? To do this we have the concept of ‘nodes’. The OSVVM co-simulation documentation does ... »
Introduction In this article I want to give some thoughts on how to model interrupts within the OSVVM co-simulation environment. The manual details how to register an interrupt callback function with the software and this is called whenever the interrupt request input (IntReq) to the CoSimTrans VHDL procedure changes with the new state. This makes the interrupt request state available to the softw... »