Reply To: Question to the OSVVM community: how to approach the methodology, learning curve

[Miroslav Marinkovic]

Hi Andrea,

Regarding your question 3):

First, you mentioned that your current VHDL testbenches write output data into a file, and then you process (offline) the obtained data vs. reference data.
In my opinion, it is better to compare output data vs. reference data directly in VHDL testbench, because you have a self-checking testbench in that case.
I am aware that this approach requires that your reference DSP model (in Matlab, C++,.. or similar) should be
“bit-true” model.

In addition to the verification task which Jim mentioned, you can do:

– If your DSP DUT have several configuration, then I assume you can have a separate pair of stimuli (input) data and reference (output) data for each DUT configuration.
Then OSVVM can help you to randomize the DUT configuration and connect each DUT configuration with the corresponding pair (stimuli, reference) in VHDL simulation.
Of course you can also randomize the stimuli data, but you have them already in a file, and they are probably already random (generated from Matlab, C++, …)

– You can randomize, for example, “data_valid_in” signal of your DSP core (probably you have it, or some similar signal)

Best regards,
Miroslav