Reply To: Xilinx not supporting VHDL anymore?

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Vivado 2022.2 simulator states to supports VHDL-2008. While this is meant to mean full support, there certainly are still many issues present. The focus was probably to support language features already supported in synthesis.

I personally tested support for VHDL-2008 fixed point number libraries, which require generic packages.

Vivado 2023.1 added VHDL-2019 support to synthesis, but not to simulation.

The Xilinx support article you mentioned discusses timing annotated netlist simulation, which is something rarely done, especially for FPGA development, it is a bit more common in ASIC development (for power estimation signal toggling waveforms). The Verilog code here is the netlist. Since this simulation is very slow, it is usually limited to few tests, so not to much effort for the user to maintain some Verilog code.