Reply To: Configuring the AXI-Lite WSTRB

[Jim Lewis]

Hi Adam,
I am not sure what that means. What are you trying to do? In Axi4Lite, strb is a byte strobe that indicates the corresponding 8 bits is part of the write. The strb will be active when Valid is active. This may be multiple clock cycles if Ready is not also active.

Does the dpRAM only accept full 32 bit writes? Maybe this device always writes 32 bits of data independent of the strb setting and that strb is totally ignored. Axi4Lite does not do bursts, so I don’t think you will see a cycle where Valid is active, but the interface does not contain any data that is valid (ie: strb is 0000). That said, if you want the dpRAM to accept AXI data only if at least one byte valid, then you could just OR all the strb bits together.

Best Regards,
Jim

P.S. The DpRam VC also has a behavioral model of a DpRam. If you try it out be sure to let us know how it goes.