Reply To: Questa Verilog/SystemVerilog Files

Why OSVVM™? Forums OSVVM Questa Verilog/SystemVerilog Files Reply To: Questa Verilog/SystemVerilog Files

#2346
Jim Lewis
Member

Hi Jake,
Just checked the Questa command reference manual. Good catch. It is an easy fix.
In the file, VendorScripts_Siemens.tcl, all of the specialization is done. In there
the analyze for Verilog/SystemVerilog is:
`tcl
proc vendor_analyze_verilog {LibraryName FileName args} {
set AnalyzeOptions [concat [CreateVerilogLibraryParams “-l “] -work ${LibraryName} {*}${args} ${FileName}]
# puts “vlog $AnalyzeOptions”
eval $::osvvm::shell vlog {*}$AnalyzeOptions
}
`
Change it to (the change follows the text CreateVerilogLibraryParams):
`tcl
proc vendor_analyze_verilog {LibraryName FileName args} {
set AnalyzeOptions [concat [CreateVerilogLibraryParams “-L “] -work ${LibraryName} {*}${args} ${FileName}]
# puts “vlog $AnalyzeOptions”
eval $::osvvm::shell vlog {*}$AnalyzeOptions
}
`
Let me know how it goes.

Best Regards,
Jim