I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.
Xilinx disreagards the fact that VHDL has certain advantages over Verilog and is the preferred HDL in Europe.
