Reply To: How to improve VHDL

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What is the primary benefit of this thread since the synthesis tool vendors will take maybe a decador or more to add simple new features for the language.

We need an effort to upgrade the flow that is used with VHDL. We need something like LLVM for VHDL. The netlist fitter can be handled by the tools. But tool for synthesis and compilation for simulation must be created through cooperation among all stakeholders.

Besides this, it must become easier to integrate high level from C/C++ or Python into VHDL testbench. This will alleviate a lot of problems since if something is not possible with VHDL then just use another language while having the peace of mind that it will integrate well.

Even if its impossible to improve VHDL practically, if it becomes possible to bind Python and C/C++, that will still be great.

What else can I say? hmmm. Ability to read ROM data from file into an RTL module. I believe this is possible for Verilog but last time I checked, it failed in Quartus with VHDL.

Hardware domain is atleast 20 years behind the software domain in the quality of tools. Many tools e.g waveform viewer of ModelSim has remained almost unchanged for maybe 20 years. I am not sure if they use GPU Hardware acceleration in their program. The GUI itself feels like it has frozen in time.