Why OSVVM™? › Forums › OSVVM › SBRD package issue with Modelsim FPGA edition › Reply To: SBRD package issue with Modelsim FPGA edition
Hi Ajeetha, Nope. That is integer’left.
Put a “wait for 0 ns” before reading the signal. That allows a simulation cycle to go by and the signal to update to the value assigned by NewID.
Jim