Reply To: Convert std_logic_vector to record

Why OSVVM™? Forums VHDL Convert std_logic_vector to record Reply To: Convert std_logic_vector to record

#2536
Jim Lewis
Member

Hi Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.

For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/

VHDL in particular is a volunteer driven standard. Hence, it is important that you do participate.

Best Regards,
Jim