Reply To: The #if in VHDL

[Hassan]

If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:

#if FEATURE1

#endif

#if FEATURE2

#if FEATURE3VER > 2

#else

#endif

#endif

How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be defined, as constants?

The ability to add or remove ports using #if in SystemVerilog is rather interesting. I believe that it does not exist in VHDL so far, maybe something like it now exists in VHDL-2019 Conditional Analysis.