Reply To: Convert std_logic_vector to record

Why OSVVM™? Forums VHDL Convert std_logic_vector to record Reply To: Convert std_logic_vector to record

#2548
Jim Lewis
Member

Yes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.

Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.