Reply To: Support for Forcing DUT Signals via OSVVM

[Jim Lewis]

If the signals you want to drive are on an interface, then your verification component can be built so that it triggers all error conditions.

If the signals you want to drive are deep in your design, you can test that capability at the level where those signals are exposed.

Alternately if signals you want are deep in the design and you want to run the test at a testbench level where those signals are buried, then you need to drive the signals using the VHDL-2008 capability for external names. This is a VHDL thing and not an OSVVM thing.

Read up on using the VHDL-2008 force capability. To successfully use the VHDL-2008 force and external name capability, I would not be surprised if your simulator required both the testbench and design be compiled using VHDL-2008.