Reply To: Safer Check if Simulation passed or Not

[Mikael]

The Report APIs should be there in Questa sim 2025.2.
The latest Questasim version is now 2025.3

Remember that today, mixed language designs are very common. Some IPs are only available in Verilog.
So it is not just VHDL assertions that can be a source of errors.
There could be SVA assertions, both immediate and concurrent.

IPs or library models written in verilog/systemverilog might have code like this:

if (false) $error("FAKE ERROR"):

Or VHDL library models can also use:

if ... then
report "FAKE ERROR" severity ERROR;

Or you might even have a UVM passive environment that monitors part of the testbench, and that is using
uvm_error(…);`

I would believe that the safe way is always to check the simulator status in the end of the simulation.
Because the simulator status is picking up all the severities of report in VHDL, Assertion fails, $error,$warning, $fatal (from verilog).

The simulator status is what we use when we run regressions using Questa Verification Run Manager.