Reply To: About function coverage of OS-VVM by vector signal
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library ieee ;
use ieee.std_logic_1164.all ;
Use ieee.std_logic_unsigned.all;
use work.CoveragePkg.all;
entity counter is
port (CLK : in std_logic ;
RST : in std_logic ;
OUTA : out std_ulogic_vector (2 downto 0)
) ;
end counter ;
architecture RTL of counter is
signal cnto :std_logic_vector(2 downto 0);
shared variable test_cover : CovPType ;
begin
test_cover.AddBins(GenBin(0,7,8));
process (CLK,RST) begin
if RST='0' then
cnto <= (others=>'0') ;
elsif (CLK'event and CLK='1') then
cnto <= cnto + '1';
end if ;
end process ;
process (CLK) begin
if (CLK'event and CLK='1') then
test_cover.ICover(to_integer_vector (cnto));
end if;
end process ;
process (CLK, cnto) begin
if (CLK'event and CLK='1') then
if (cnto="111") then
test_cover.WriteCovDb ("test_cover.txt", OpenKind => WRITE_MODE );
test_cover.WriteBin;
end if ;
end if;
end process ;
OUTA <= cnto;
end RTL ;