Reply To: About function coverage of OS-VVM by vector signal
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Two issues with your code:
- You are using ‘std_logic_unsigned‘ package which can cause serious problems when mixed with VHDL-2008 code. Long story short: if your system contains ‘std_logic_unsigned‘ precompiled in VHDL-2002 mode and you try to use it together with OS-VVM packages compiled in VHDL-2008 mode, logic types internal markers in the libraries will be incompatible in both. You may get no errors/warnings during your design compilation, or receive confusing messages stating that subprograms cannot be found for given argument types. Please use NUMERIC_STD_UNSIGNED that was added to VHDL-2008 specifically for the same purposes as ‘std_logic_unsigned‘, but avoids numerous problems in the older package.
- Once you replace package in the design unit header, there is one more issue left: you are creating 8 INTEGER bins, so the data sampled in the data collection process should be INTEGER, not INTEGER_VECTOR. Please replace
After those two changes you should get correct results.
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