Reply To: external name for a signal inside record type

Why OSVVM™? Forums VHDL external name for a signal inside record type Reply To: external name for a signal inside record type

#1312
fdominguez
Member

I follow the 2-process method from Gaisler and I had the same error with Modelsim. The report message was:

“Illegal external name. ‘uut.r.state_top’ denotes an element of an array or record.”

I took your advice in mind, I moved my record definition to a package and then I added this code to testbench:

alias uut_r_register is << signal uut.r : fsm_wg_control_regs_t >>;  

alias uut_state_top is uut_r_register.state_top;

It works well!