Reply To: failure to compile a Scoreboard in Modelsim DE using osvvm 2018.04
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Hi Jim, Many thanks for your answer. My problem is that i have tried every which way to get things to compile and i always get errors.
My scoreboard generic package is defined like this now in a seperate design unit (i.e. a VHDL file):
package ScoreBoardPkg_IPv4Pkg is new ScoreBoardGenericPkg
generic map (
ExpectedType => ETHER_IPv4_ESP_TYPE,
ActualType => ETHER_IPv4_ESP_TYPE,
match => ETHER_IPv4_ESP_MATCH,
expected_to_string => ETHER_IPv4_ESP_TYPE_to_string,
actual_to_string => ETHER_IPv4_ESP_TYPE_to_string
In my testbench i reference my new package instance like this
And i am wondering where do i make the instantiation ? I have tried like this in my testbench :
architecture Behavioral of osvvm_testbench is
And when compiling my design in Modelsim i get this error
— Loading package ScoreboardGenericPkg
# ** Error: /home/barry2/vivado_projects/packetDecoder200G/packetDecoder200G/packetDecoder200G.srcs/sim_1/new/osvvm_testbench.vhd(45): A member of an uninstantiated package is referenced outside the scope of the package.
# — Loading package design_package
# — Loading context declaration OsvvmContext
# — Loading package osvvm_testbench_pkg
# ** Error: /home/barry2/vivado_projects/packetDecoder200G/packetDecoder200G/packetDecoder200G.srcs/sim_1/new/osvvm_testbench.vhd(65): VHDL Compiler exiting
# End time: 08:43:03 on Aug 01,2018, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# ** Error: /home/barry2/msim32bit/modelsim_dlx/linuxpe/vcom failed.
So i don’t understand why i get this error because i (think !) that i have instantiated my new scoreboard package based on ScoreboardGenericPkg in my design unit : ScoreBoardPkg_IPv4Pkg.vhd
and this package does compile fine…i have implemented some functions for the match, expected_to_string and actual_to_string ports and i have referenced this new instantiation with my include clause.
Can you please help explain where i am going wrong Jim ?