Why OSVVM™? › Forums › VHDL › Generic packages, unconstrained types and access types › Reply To: Generic packages, unconstrained types and access types
I tried your advice, now Modelsim prints a error message, which says more about the real problem it has with the code:
#** Fatal: (vsim-3420): Array lengths do not match. Left is (UNDEFINED) (UNCONSTRAINED ARRAY). Right is 0 (1 to 1)
So it seems. that Modelsim cannot handle assignments of constrained strings to a object of unconstrained string type. With unconstrained std_logic_vectors for the data record item, it works.