Reply To: How to improve VHDL
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*Many people have been using for years the following three
Packages in almost any code they write:
— classic package of Synopsys in old VHDL
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
They make it possible to execute unsigned math operations on vectors
in a convenient way with out all the clumsy casting operations
or conversions needed when you use other vector-math packages.
In VHDL-200 finally the previous 3 packages have been replaced with
the new standard packages, and the last package is more powerful
(for example enable division operations and more…).
— same trio declarations with new package of IEEE in VHDL-2008
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std_unsigned.all ; — a new package !
This is very nice, but I can not find a replacement for the
Following useful trio:
— the signed trio
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_signed.all ;
Which enable signed math (for example when you want to
make a compare operation and may other applications).