Reply To: How to improve VHDL

Why OSVVM™? Forums VHDL How to improve VHDL Reply To: How to improve VHDL

Andy Jones


1st issue: I have seen very few designs that use a signed numeric interpretation of every std_logic_vector in the design. Most designs that use signed interpretation also use unsigned interpretations, which would not be possible if such a package were used. If you need signed interpretations, it is best to use either integer subtypes or explicit signed data types to clearly define where signed interpretations and arithmetic are desired.

2nd issue: Unlike the mathematical operators that have a widely accepted operator precedence, boolean operators do not. Therefore explicitly defining the desired precedence of boolean operators using parentheses provides an unambiguous description of the desired result. When you wrote “a or b and c” I had no idea whether you meant “(a or b) and c” or “a or (b and c)”. 

Think less about how little you can type, and more about how clearly you can express the desired behavior. Those who will have to review, reuse or maintain your design will thank you for it.